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? semiconductor components industries, llc, 2010 july, 2010 ? rev. 2 1 publication order number: adm1033/d adm1033 thermal monitor and fan speed (rpm) controller the adm1033 is a one channel remote ? and local ? temperature sensor and fan controller. the remote channel monitors the temperature of the remote thermal diode, which may be discrete 2n3904/6s or may be located on a microprocessor die. the device also monitors its own ambient temperature. the adm1033 can monitor and control the speed of cooling fan. the user can program a target fan speed, or else use the look ? up table to input a temperature ? to ? fan speed profile. the look ? up table can be configured to run the fans at discrete speeds (discrete mode) or to ramp the fan speed with temperature (linear mode). the adm1033 communicates over a 2 ? wire smbus 2.0 interface. an 8 ? level location input allows the user to choose between smbus 1.1 and smbus 2.0. an alert output indicates error conditions. t he therm i/o signals overtemperature as an output and times therm assertions as an input. pin 8 can be configured as a reference for the therm (prochot ) input. features ? 1 local and remote temperature channels ? 1 c accuracy on local and remote channels ? automatic remote temperature channel, up to 1 k ? fast (up to 64 measurements per second) ? smbus 2.0, 1.1, and 1.0 compliant ? smbus address input/location input to udid ? programmable over/undertemperature limits ? programmable fault queue ? smbusalert output ? fail ? safe overtemperature comparator output ? fan speed (rpm) controller ? look ? up table for temperature ? to ? fan speed control ? linear and discrete options for look ? up table ? fan_fault output ? therm input, used to time prochot assertions ? ref input, used as reference for therm (prochot ) ? 3.0 v to 5.5 v supply ? small 16 ? lead qsop package ? this is a pb ? free device applications ? desktop and notebook pcs ? embedded systems ? telecommunications equipment ? lcd projectors http://onsemi.com pin assignment (top view) 1 2 3 4 5 6 7 8 14 13 12 11 10 9 tach1 comp nc therm v cc gnd drive1 sda location nc nc scl adm1033 fan_fault/ref alert d1 ? d1+ 16 15 see detailed ordering and shipping information in the package dimensions section on page 34 of this data sheet. ordering information xxx = specific device code # = pb ? free package yy = date code ww = work week marking diagram 1 1033a rqz #yyww qsop ? 16 case 492 alert
adm1033 http://onsemi.com 2 figure 1. functional block diagram tach alert comp therm adc gnd 6 vcc drive adm1033 location d ? d+ therm percent timer fan_fault ref alert therm sda scl conversion rate register offset registers value and limit registers limit comparator address pointer register serial bus interface configuration registers fault queue hysteresis registers smbus address status register smbusalert mask registers fault queue 10 9 11 12 nc nc 2 1 13 8 3 7 8 15 16 14 5 bandgap reference bandcap temperature sensor src block manual fan speed control registers temperature to fan speed lookup table rpm fan speed controller enhance acoustics fan speed counter signal conditioning analog multiplexer nc = no connect
adm1033 http://onsemi.com 3 absolute maximum ratings parameter rating unit positive supply voltage (v cc ) ? 0.3, +6.5 v voltage on any input or output pin except fan_fault and location ? 0.3 to v dd +6.5 v voltage on fan_fault (note 1) v cc voltage on location v cc + 0.3 v input current at any pin 20 ma maximum junction temperature (t j max) 150 c storage temperature range ? 65 to +150 c lead temperature, soldering (10 s) 300 c ir reflow peak temperature 220 c esd rating ? all pins 1500 v 1. during powerup the voltage on fan_fault should not be higher than v cc . stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. note: this device is esd sensitive. use standard esd precautions when handling. thermal characteristics parameter rating 16 ? lead qsop package ja = 150 c/w, jc = 39 c/w pin assignment pin no. mnemonic description 1 drive1 drive1 pin drives fan 1. open ? drain output. requires a pullup resistor. 2 tach1 fan 1 fan speed measurement input. connects to the fan?s tach output to measure the fan speed. 3 alert comp open ? drain active low output. assets low whenever a measurement goes outside its programmed limits if not masked. automatically goes high again when the measured parameter falls back within its limits. 4 nc no connect. 5 gnd ground for analog and digital circuitry. 6 vcc power. can be powered by 3.3 v standby power if monitoring in low power states is required. 7 therm can be configured as an overtemperature interr upt output, or as an input (to monitor prochot output of an intel cpu). a timer meas ures assertion times on the therm pin (either input or output). 8 fan_fault /ref fan_fault : open ? drain output. asserted low when one or both fans stall. requires a pullup resistor to v cc . ref: analog input reference for the therm input. 9 d1 ? cathode connection for the first thermal diode or diode ? connected transistor. 10 d1+ anode connection for the first thermal diode or diode ? connected transistor. 11 nc no connect. 12 nc no connect. 13 location 8 ? level analog input. used to determine the correct smbus version and the smbus address (in fixed and discoverable mode) and to set the lll bits in the udid (in arp ? capable mode). 14 alert open ? drain output. smbusalert pin. alerts the system in the case of out ? of ? limit events, such as over temperature. can be configured as sticky smbus mode or comparator mode. 15 sda serial bus bidirectional data. connects to the smbus master?s data line. requires pullup resistor if not provided elsewhere in the system. 16 scl serial smbus clock input. connects to the smbus master?s clock line. requires pullup resistor if not already provided in the system.
adm1033 http://onsemi.com 4 electrical characteristics (t a = t min to t max , v cc = v min to v max , unless otherwise noted. (note 1) parameter test conditions / comments min typ max unit power supply supply voltage, v cc (note 2) 3.0 3.30 3.6 v supply current, i cc interface inactive, adc active 3.0 ma standby mode 900 a undervoltage lockout threshold 2.5 v power ? on reset threshold 1.0 2.4 v temperature ? to ? digital converter internal sensor accuracy 20 c t a 60 c ? 40 c t a +100 c ? 4.0 1.0 2.0 +2.0 c resolution 0.03125 c external diode sensor accuracy ? 40 c t d +100 c; t a = +40 c ? 40 c t d +100 c; +20 c t a +60 c ? 40 c t d +100 c; ? 40 c t a +100 c ? 3.0 0.5 1.0 1.0 1.25 +2.0 c resolution 0.03125 c remote sensor source current high level mid level low level 85 34 5.0 a series resistance cancellation 1000 power supply sensitivity 1.0 %/v conversion time (local temperature) averaging enabled 11 ms conversion time (remote temperature) averaging enabled 32 ms total conversion time averaging enabled 43 ms open ? drain digital outputs (alert , therm , fan_fault , drive1, drive2) (note 3) output low voltage, v ol i out = ? 6.0 ma; v cc = +3.0 v 0.4 v high level output leakage current, i oh v out = v cc ; v cc = 3.0 v 0.1 1.0 a digital input leakage current (tach1, tach2) input high current, i ih ? v in = v cc ? 1.0 a input low current, i il v in = 0 1.0 a input capacitance, c in 7.0 pf digital input logic levels (tach1, tach2) input high voltage, v ih 2.0 5.5 v input low voltage, v il ? 0.3 +0.8 v hysteresis 500 mv p ? p open ? drain serial data bus output (sda) output low voltage, v ol i out = ? 6.0 ma; v cc 0.4 v high level output leakage current, i oh v out = v cc 0.1 1.0 a serial bus digital inputs (scl, sda) input high voltage, v ih 2.1 v input low voltage, v il 0.8 v hysteresis 500 mv analog inputs (location, ref) input resistance 80 125 160 k 1. typicals are at t a = 25 c and represent most likely parametric norm. standby current typ. is measured with v cc = 3.3 v. timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.1 v for a rising edge. 2. operation at 5.5 v is guaranteed by design, not production tested. 3. recommend use of 100 k pullup resistors for all open ? drain outputs from the adm1033. 4. guaranteed by design, not production tested. 5. smbus timeout disabled by default. see the smbus section for more information.
adm1033 http://onsemi.com 5 electrical characteristics (t a = t min to t max , v cc = v min to v max , unless otherwise noted. (note 1) parameter unit max typ min test conditions / comments tachometer accuracy fan speed measurement accuracy 4.0 % agtl + input (therm ) input high level 0.75 x ref v input low level 0.4 v serial bus timing (note 4) clock frequency, f sclk see figure 2 400 khz glitch immunity, t sw see figure 2 50 ns bus free time, t buf see figure 2 1.3 s start setup time, t su:sta see figure 2 0.6 s start hold time, t hd:sta see figure 2 0.6 s stop condition setup time t su:sto see figure 2 0.6 s scl low time, t low see figure 2 1.3 s scl high time, t high see figure 2 0.6 s scl, sda rise time, t r see figure 2 1000 ns scl, sda fall time, t f see figure 2 300 ns data setup time, t su:dat see figure 2 100 ns detect clock low timeout, t timeout see note 5 25 35 ms 1. typicals are at t a = 25 c and represent most likely parametric norm. standby current typ. is measured with v cc = 3.3 v. t iming specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.1 v for a rising edge. 2. operation at 5.5 v is guaranteed by design, not production tested. 3. recommend use of 100 k pullup resistors for all open ? drain outputs from the adm1033. 4. guaranteed by design, not production tested. 5. smbus timeout disabled by default. see the smbus section for more information. figure 2. serial bus timing diagram p s t low t r t f t hd:sta t hd:dat t su:dat t su:sta t hd:sta t su:sto t high scl ps sda t buf
adm1033 http://onsemi.com 6 typical characteristics figure 3. temperature error vs. pcb track resistance dxp to gnd and v cc figure 4. remote temperature error vs. d+, d ? capacitance figure 5. remote temperature error vs. series resistance on d+ and d ? figure 6. remote temperature error vs. power supply noise frequency figure 7. remote temperature error vs. common ? mode noise frequency coupled on d+ and d ? figure 8. remote temperature error vs. differential mode noise frequency coupled on d+ and d ? leakage resistance (m ) temperature error ( c) 40 20 ?20 0 ?60 ?40 ?100 ?80 0 102030 40 5060 708090100 d+ to gnd d+ to v cc capacitance (nf) temperature error ( c) 0 ?10 ?30 ?20 ?60 ?70 ?40 ?50 ?80 04 2681012 dev 33 ( c) dev 32 ( c) dev 31 ( c) series resistance in d+/d? lines (k ) temperature error ( c) 100 90 80 70 60 50 40 30 20 10 0 ?10 12 3 4 6 5 dev 31 dev 32 dev 33 noise frequency (hz) temperature error ( c) 50 45 40 35 30 25 20 15 10 5 00 01m2m 4m 3m 5m 6m 20mv 50mv 100mv noise frequency temperature error ( c) 4.0 3.5 3.0 2.5 1.5 2.0 1.0 0.5 0 01m 3m 2m 5m 4m 6m 10mv 20mv temperature error ( c) 20 15 10 5 0 ?5 ?10 01m2m3m4m 6m 5m ext 100mvpp ext 250mvpp
adm1033 http://onsemi.com 7 typical characteristics figure 9. remote 1 temperature error vs. actual temperature figure 10. local temperature error vs. actual temperature figure 11. standby supply current vs. sclk frequency figure 12. standby supply current vs. supply voltage fscl (khz) i cc ( a) 430 420 410 400 390 380 370 360 1 10 1000 100 dev 33 dev 32 dev 31 supply voltage (v) standby supply current 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 02 6 45 3 1 figure 13. supply current vs. conversion rate figure 14. supply current vs. adm1033 temperature conversion rate (hz) i cc ( a) 1200 1000 800 600 400 200 0 0.01 0.1 1 100 10 dev 33 dev 32 dev 31 temperature ( c) supply current 1.55 1.50 1.45 1.40 1.35 1.30 1.25 ?60 ?40 ?20 0 100 40 60 80 20 s1 s2 s3 s4 s5 v1 v2 v3 v4 v5 diode temperature ( c) temperature error ( c) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?60 ?40 ?20 0 80 100 120 40 60 20 140 mean high 4 sigma low 4 sigma s1 s2 s3 s4 s5 v1 v2 v3 v4 v5 temperature ( c) error ( c) 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?50 0 100 50 150 mean high 4 sigma low 4 sigma
adm1033 http://onsemi.com 8 functional description the adm1033 is a local ? and remote ? temperature monitor and fan controller for use in a variety of applications, including microprocessor ? based systems. the device accurately monitors remote and ambient temperature and uses that information to quietly control the speed of a cooling fan. whenever a fan stalls, the device asserts a fan_fault output. the adm1033 features a therm i/o. as an input, this measures assertions on the therm pin. as an output, it asserts a low signal to indicate when the measured temperature exceeds the programmed therm temperature. the adm1033 communicates over an smbus 2.0 interface. its location input determines which version of smbus to use, as well as the smbus address (in fixed and discoverable mode) and the location bits in the udid (in arp ? capable mode). internal registers table 1 gives a brief description of the adm1033?s principal internal registers. for more detailed information on the function of each register, refer to table 31. serial bus interface the adm1033 communicates with the master via the 2 ? wire smbus 2.0 interface. it supports two versions of smbus 2.0, determined by the value of the location input?s resistors. the first version is fully arp ? capable. this means that it supports address resolution protocol (arp), allowing the master to dynamically address the device on powerup. it responds to arp commands such as ?prepare to arp.? the second smbus version, fixed and discoverable, is backwards compatible with smbus 1.0 and 1.1. in this mode, the adm1033 powers up with a fixed address, which is determined by the state of the location pin on powerup. note: when using the adm1033, addresses 0xc2 and 0xca should not be used by any other device on the bus. location input the location input is a resistor divider input. it has multiple functions and can specify the smbus version (in fixed and discoverable or arp ? capable modes); the smbus address (in fixed and discoverable mode); and the lll bits (in udid in arp ? capable mode). the voltage of this 8 ? level input is set by a potential divider. the voltage on location is sampled on powerup and digitized by the on ? chip adc to determine the location input value. because the location input is sampled only at powerup, changes made while power is applied have no effect. figure 15. bootstrapping the location input v cc gnd adm1033 r1 r2 location pin 13 smbus 2.0 arp ? capable mode in arp ? capable mode, the adm1033 supports features such as address resolution protocol (arp) and unique device identifier (udid). the udid is a 128 ? bit message that describes the adm1033?s capabilities to the master. the udid also includes a vendor specific id for functionally equivalent devices. figure 16. setting up multiple adm1033 addresses in smbus 2.0 arp ? capable mode v cc 1.5k 1k 1k 1k 1k 1k 1.5k gnd adm1033 1 adm1033 2 adm1033 3 adm1033 5 adm1033 7 arp location = 111 arp location = 110 adm1033 4 arp location = 101 arp location = 100 adm1033 6 fd address = 53h fd address = 52h adm1033 8 fd address = 51h fd address = 50h in smbus 2.0 mode, this vendor specific id is generated by an on ? chip random number generator. this should enable two adjacent adm1033s in the same system to powerup with a different vendor specific id, allowing the master to identify the two separate adm1033?s and assign a dif ferent address to each. the state of the location input on powerup is also reflected in the udid. this is useful when there is more than one adm1033 in the system, so the master knows which one it is communicating with. the complete udid is listed in table 3. the smbus 2.0 master issues both general and directed arp commands. a general command is directed at all arp devices. a directed command is targeted at a single device once an address has been established. the pec byte must be used for arp commands. (refer to the packet error checking (pec) section.) the adm1033 responds to the following commands: ? prepare to arp (general) ? reset device (general and directed) ? get udid (general and directed) ? assign address (general)
adm1033 http://onsemi.com 9 table 1. internal register descriptions register description configuration provides control and configuration of various functions on the device. conversion rate determines the number of measurements per second completed by the adm1033. address pointer contains the address that selects one of the other internal registers. when writing to the adm1033, the first byte of data is always a register address, written to the address pointer register. status provides the status of each limit comparison. interrupt mask allows the option to mask alert s due to particular out ? of ? limit conditions. value and limit stores the results of temperature and fan speed measurements, along with their limit values. offset allows the local and remote temperature channel readings to be offset by a twos complement value written to them. these values are automatically added to the temperature values (or subtracted from them if negative). this allows the systems designer to optimize the system if required, by adding or subtracting up to 15.875 c from a temperature reading. therm limit and hysteresis contains the temperature value at which therm is asserted and indicates the level of hysteresis. look ? up table used to program the look ? up table for the fan speed ? to ? temperature profile. therm % on ? time and therm % limit reflects the state of the therm input and monitors the duration of the assertion time of the signal as a percentage of a time window. the user can program the length of the time window. table 2. resistor ratios for setting location bits ideal ratio r2/(r1 + r2) r1 k r2 actual r2/(r1 + r2) error % smbus ver (note 1) smbus address udid lll n/a 0 o/c 1 0 arp n/a 111 0.8125 18 82 0.82 +0.75 arp n/a 110 0.6875 22 47 0.6812 ? 0.63 arp n/a 101 0.5625 12 15 0.5556 ? 0.69 arp n/a 100 0.4375 15 12 0.4444 +0.69 fd 0x53 n/a 0.3125 47 22 0.3188 +0.63 fd 0x52 n/a 0.1875 82 18 0.18 ? 0.75 fd 0x51 n/a n/a o/c 0 0 0 fd 0x50 n/a 1. arp denotes arp ? capable mode, fd denotes fixed and discoverable mode. table 3. udid values bit no. name function value <127:120> device capabilities describes the adm1033?s capabilities (for instance, that it supports pec and uses a random number address device). 11000001 <119:112> version/revision udid version number (version 1) and silicon revision identification 00001010 <111:96> vendor id analog devices vendor id number, as assigned by the sbs implementer?s forum or the pci sig. 00010001 11010100 <95:80> device id device id. 00010000 00110100 <79:64> interface identifies the protocol layer interfaces supported by the adm1033. this represents smbus 2.0 as the interface version.. 00000000 00000100 <63:48> subsystem vendor id subsystem vendor id = 0 (subsystem fields are unsupported). 00000000 00000000 <47:32> subsystem device id subsystem device id = 0 (subsystem fields are unsupported). 00000000 00000000 <31:0> vendor specific id a unique number per device. contains location information (ll) and a 16 ? bit random number (x). see table 5 for information on setting the lll bits. 00000000 00000lll xxxxxxxx xxxxxxxx
adm1033 http://onsemi.com 10 smbus 2.0 fixed and discoverable mode the adm1033 also supports fixed and discoverable mode, which is backwards compatible with smbus 1.0 and 1.1. fixed and discoverable mode supports all the same functionality as arp ? capable mode, except for assign address in which case it powers up with a fixed address and is not changed by the assign address call. the fixed address is determined by the state of the location pin on powerup. smbus 2.0 read and write operations the master initiates data transfer by establishing a start condition, defined as a high ? to ? low transition on the serial data line (sda) while the serial clock line (scl) remains high. this indicates that an address/data stream is to follow. all slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, which consist of a 7 ? bit address (msb first) plus an r/w bit. this last bit determines the direction of the data transfer (whether data is written to or read from the slave device). 1. the peripheral that corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, which is known as the acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is a 0, the master writes to the slave device. if the r/w bit is a 1, the master reads from it. 2. data is sent over the serial bus in sequences of 9 clock pulses ? 8 bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low ? to ? high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. this is known as no acknowledge. the master takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot be changed without starting a new operation. to write data to one of the device data registers or to read data from it, the address pointer register (apr) must be set so that the correct data register is addressed; then data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the apr. if data is to be written to the device, then the write operation contains a second data byte, which is written to the register selected by the apr. as illustrated in figure 17, the device address is sent over the bus, followed by r/w set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to be written to, which is stored in the apr. the second data byte is the data to be written to the internal data register. when reading data from a register there are two possibilities. if the adm1033?s apr value is unknown or incorrect, it must be set to the correct value before data can be read from the desired data register. to do this, perform a write to the adm1033 as before, but send only the data byte containing the register. (see figure 18.) a read operation is then performed, using the serial bus address and the r/w bit set to 1, followed by the data byte read from the data register. (see figure 19.) however, if the apr is already at the desired address, data can be read from the corresponding data register without first writing to the apr. in this case, see figure 18 can be omitted. in figure 17 to figure 19, the serial bus address is determined by the state of the location pin on powerup. figure 17. writing a register address to the address pointer register, then writing data to the selected register start by master stop by master ack. by adm1033 ack. by adm1033 ack. by adm1033 a6 119 9 a5 a4 a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 scl sda frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte sda (continued) scl (continued) 9 1 d7 d6 d5 d4 d3 d2 d1 d0
adm1033 http://onsemi.com 11 figure 18. writing to the address pointer register only (send byte) figure 19. reading data from a previously selected register stop b y master ack. by adm1033 ack. by adm1033 start by master scl 119 9 frame 1 serial bus address byte frame 2 address pointer register byte a6 a5 a4 a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 sda stop b y master start by master ack. by adm1033 no ack. by adm1033 r/w scl 119 9 sda a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 frame 1 serial bus address byte frame 2 data byte from adm1034 register addresses for single/block byte modes the adm1033 supports single byte as well as block read and write operations. the register address determines whether a single byte or multiple byte (block) operation is run. for a single byte operation, the msb of the register address is set to 0; for a multiple byte operation, it is set to 1. the number of bytes read in a multiple byte operation is set in the #bytes/block read register at address 0x00. the number of bytes written to the adm1033 is specified during the block write operation. the addresses quoted in the register map and throughout this data sheet assume single byte operation. for multiple byte operations, set the msb of each register address to 1. write operations the smbus specifications define protocols for read and write operations. the adm1033 supports send byte, write byte, and block byte smbus write protocols. the following abbreviations are used in the diagrams: s?start p?stop r?read w?write a?acknowledge a ?no acknowledge send byte in this operation, the master device sends a single ? command byte to a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends a 7 ? bit address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends the register address. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda, and the transaction ends. figure 20. send byte slave address s reg address w a a p the adm1033 uses the send byte operation to write a register address to the apr for a subsequent read from the same address. (see figure 24.) the user may be required to read data from the register immediately after setting up the address. if so, the master can assert a repeat start condition immediately after the final ack and carry out a single byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a register address and one data byte to the slave device as follows: 1. the master asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by a write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends the register address. the msb of the register address should equal 0 for a write byte operation. if the msb equals 1, a block write operation takes place. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. figure 21. write byte operation slave address s reg address data w a a a p
adm1033 http://onsemi.com 12 block write in this operation, the master device writes a block of data to a slave address as follows. a maximum of 32 bytes can be written. 1. the master asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by a write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends the register address. the register address sets up the address pointer register and determines whether a block write (msb = 1) or a byte write (msb = 0) takes place. 5. the slave asserts ack on sda. 6. the master sends the byte count. 7. the slave asserts ack on sda. 8. the master sends n data bytes. 9. the slave asserts ack on sda after each byte. 10. the master asserts a stop condition on sda to end the transaction. figure 22. block write to ram slave address s byte count data 2 data 1 register address w a a p a a adata n a read operations receive byte this is useful when repeatedly reading a single register. the register address must be set up prior to this, with the msb at 0 to read a single byte. in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master sends no ack on sda. 6. the master asserts a stop condition on sda, and the transaction ends. in the adm1033, the receive byte protocol is used to read a single byte from a register whose address has previously been set by a send byte or write byte operation. figure 23. receive byte slave address s data r a a p block read in this operation, the master reads a block of data from a slave device. the number of bytes to be read must be set in advance. to do this, use a write byte operation to the #bytes/block read register at address 0x00. the register address determines whether a block ? read or a read ? byte operation is to be completed (set msb to 1 to specify a block ? read operation). a maximum of 32 bytes can be read. 1. the master asserts a start condition on sda. 2. the master sends the 7 ? bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends the register address (msb = 1). 5. the slave asserts ack on sda. 6. the master asserts a repeated start on sda. 7. the master sends the 7 ? bit slave address followed by the read bit (high). 8. the slave asserts ack on sda. 9. the slave sends the byte count. 10. the master asserts ack on sda. 11. the slave sends n data bytes. 12. the master asserts ack on sda after each data byte. 13. the master does not acknowledge after the nth data byte. 14. the master asserts a stop condition on sda to end the transaction. figure 24. block read from ram slave address s byte count data 1 register address w a p a a adata n slave address s r a a smbus timeout the adm1033 has a programmable smbus timeout feature. when this is enabled, the smbus typically times out after 25 ms of no activity. the timeout is disabled by default. it prevents hangups by releasing the bus after a period of inactivity. to enable the sda timeout, set the sda timeout bit (bit 5) of configuration register 1 (address 0x01) to 1. to enable the scl timeout, set the scl timeout bit (bit 4) of configuration register 1 (address 0x01) to 1. packet error checking (pec) the adm1033 also supports packet error checking (pec). this optional feature is triggered by the extra clock for the pec byte. the pec byte is calculated using crc ? 8. the frame check sequence (fcs) conforms to crc ? 8 by the following: (eq. 1) c(x) x 8 x 2 x 1 for more information, consult www.smbus.org. alert response address (ara) figure 25. alert response address alert response address s device address r a a p when multiple devices exist on the same bus, the ara feature allows an interrupting device to identify itself to the host. the alert output can be used as an interrupt output or as an smbusalert . one or more alert outputs can be connected to a common smbusalert line, connected to the master.
adm1033 http://onsemi.com 13 if a device?s alert line goes low, the following occurs: 1. smbusalert is pulled low. 2. the master initiates a receive byte operation and sends the alert response address (ara 0001 100). this is a general call address that must not be used as a specific address. 3. the device with the low alert output responds to the ara, and the master reads its device address. once the address is known, it can be interrogated in the usual way. 4. if low alert output is detected in more than one device, the one with the lowest device address has priority, in accordance with normal smbus arbitration. 5. once the adm1033 has responded to the ara, it resets its alert output. however, if the error persists, the alert is re ? asserted on the next monitoring cycle. temperature measurement system internal temperature measurement the adm1033 contains an on ? chip band gap temperature sensor. the on ? chip adc performs conversions on the sensor?s output, outputting the data in 13 ? bit format. the resolution of the local temperature sensor is 0.03125 c. table 4 shows the format of the temperature data msbs. table 5 shows the same for the lsbs. to ensure accurate readings, read the lsbs first. this locks the current lsbs and msbs until the msbs are read. they then start to update again. (reading only the msbs does not lock the registers.) temperature updates to the look ? up table take place in parallel; so fan speeds may be updated even if the msbs are locked. table 4. temperature data format ? (local temperature and remote temperature high bytes) temperature ( c) digital output ? 64 c 0000 0000 ? 40 c 0001 1000 ? 32 c 0010 0000 ? 2 c 0011 1110 ? 1 c 0011 1111 0 c 0100 0000 1 c 0100 0001 2 c 0100 0010 10 c 0100 1010 20 c 0101 0100 50 c 0111 0010 75 c 1000 1011 100 c 1010 0100 125 c 1011 1101 150 c 1101 0110 191 c 1111 1111 table 5. local and remote sensor extended resolution extended resolution ( c) temperature low bits 0.0000 00000 0.03125 00001 0.0625 00010 0.125 00100 0.250 01000 0.375 01100 0.500 10000 0.625 10100 0.750 11000 0.875 11100 temperature ( c) = (msb ? 64 c) + (lsb x 0.03125) example: msb = 0101 0100 = 84d lsb = 11100 = 28 temperature c = (84 ? 64) + (28 x 0.03125) = 20.875 remote temperature measurement the adm1033 can measure the temperature of external diode sensor or diode ? connected transistor, which are connected to pins 9 and 10. these pins are dedicated temperature input channels. the series resistance cancellation (src) feature can automatically cancel out the effect of up to 1 k of resistance in series with the remote thermal diode. the forward voltage of a diode or diode ? connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about ? 2 mv/ c. unfortunately, the absolute value of v be varies from device to device, and individual calibration is required to null this out. therefore, the technique is unsuitable for mass production. figure 26. measuring temperature by using discreet transistors adm1033 2n3904 d+ d? adm1033 2n3906 d+ d? the adm1033 operates at three different currents to measure the change in v be . figure 27 shows the input signal conditioning used to measure the output of an external temperature sensor. it also shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. the external sensor could work equally well as a discrete transistor. if a discrete transistor is used, the collector is not grounded, and should be linked to the base. if a pnp transistor is used, the base is connected to the d ? input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d ? input and the base to the d+ input.
adm1033 http://onsemi.com 14 if the sensor is used in a very noisy environment, a capacitor value up to 1000 pf may be placed between the d+ and d ? inputs to filter the noise. however, additional parasitic capacitance on the lines between d+, d ? , and the thermal diode should also be considered. the total capacitance should never be greater than 1000 pf. to measure each v be , the sensor is switched between operating currents of i, (n1 x i), and (n2 x i). the resulting waveform is passed through a 65 khz low ? pass filter to remove noise, then to a chopper ? stabilized amplifier that amplifies and rectifies the waveform. this produces a dc voltage proportional to v be . these voltage measurements determine the temperature of the thermal diode, while automatically compensating for any series resistance on the d+ and/or d ? lines. the temperature is stored in two registers as a 13 ? bit word. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles at conversion rates of less than or equal to 8 hz. an external temperature measurement takes nominally 32 ms when averaging is enabled and 6 ms when averaging is disabled. one lsb of the adc corresponds to 0.03125 c. the adm1033 can theoretically measure temperatures from ? 64 c to +191.96875 c, although these are outside its operating range. the extended temperature resolution data format is shown in table 5. the data for the local and remote channels is stored in the extended temperature resolution registers (reg. 0x40 = local, reg. 0x42 = remote 1). table 6. temperature measurement registers register description default 0x40 local temperature, lsbs 0x00 0x41 local temperature, msbs 0x00 0x42 remote 1 temperature, lsbs 0x00 0x43 remote 1 temperature, msbs 0x00 high and low temperature limit registers are associated with each temperature measurement channel. exceeding the programmed high and low limits sets the appropriate status bit. exceeding either limit can cause an smbusalert interrupt. table 7. temperature measurement limit registers register description default 0x0b local high limit 0x8b (75 c) 0x0c local low limit 0x54 (20 c) 0x0d local therm limit 0x95 (85 c) 0x0e remote 1 high limit 0x8b (75 c) 0x0f remote 1 low limit 0x54 (20 c) 0x10 remote 1 therm limit 0x95 (85 c) figure 27. adm1033 signal conditioning d+ d? remote sensing transistor i n1 i n2 ii bias v dd v out+ to adc v out? low ? pass filter f c = 65khz additional functions several other temperature measurement functions available on the adm1033 of fer the systems designer added flexibility. turn ? off averaging the adm1033 performs averaging at conversion rates of less than or equal to 8 conversions per second. this means that the value in the measurement register is the average of 16 measurements. for faster measurements, set the conversion rate to 16 conversions per second or greater. (averaging is not carried out at these conversion rates.) alternatively, switch off averaging at the slower conversion rates by setting bit 1 (avg) of configuration 1 register (address 0x01). single ? channel adc conversions in normal operating mode, the adm1033 converts on two temperature channels: the local temperature channel, and the remote channel. however, the user has the option to set up the adm1033 to convert on one channel only. to enable single ? channel mode, the user sets the round ? robin bit (bit 7) in configuration register 2 (address 0x02) to 0. when the round ? robin bit equals 1, the adm1033 converts on all temperature channels. in single ? channel mode, it converts on one channel only, to be determined by the state of the channel selector bits (bits 5 and 4) of the configuration register 2 (address 0x02).
adm1033 http://onsemi.com 15 table 8. channel selector bits 5:4 channel selector (configuration 2) 00 local channel = default 01 remote 1 channel 10 reserved 11 reserved removing temperature errors as cpus run faster and faster, it gets more difficult to avoid high frequency clocks when routing the d+ and d ? traces around a system board. even when the recommended layout guidelines are followed, temperature errors attributed to noise coupled onto the d+ and d ? lines remain. high frequency noise generally gives temperature measurements that are consistently too high. the adm1033 has local and remote temperature offset registers at 0x16 and 0x17; one for each channel. by completing a one ? time calibration, the user can determine the offset caused by the system board noise and remove it using the offset registers. the registers automatically add a twos compliment word to the remote temperature measurements, ensuring correct readings in the value registers. table 9. offset registers registration description default 0x16 local offset 0x00 0x17 remote 1 offset 0x00 table 10. offset register values code offset value 0 0000 000 0 c (default value) 0 0000 001 0.125 c 0 0000 111 0.875 c 0 0001 111 1.875 c 0 0111 111 7.875 c 0 1111 111 15.875 c 1 0000 000 ? 16 c 1 1111 000 ? 0.875 c layout considerations digital boards can be electrically noisy environments. try to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. take the following precautions: ? place the adm1033 as close as possible to the remote sensing diode. a distance of 4 inches to 8 inches is adequate, provided that the worst noise sources such as clock generators, data/address buses, and crts are avoided. ? route the d+ and d ? tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. ? use wide tracks to minimize inductance and reduce noise pickup. at least 5 mil track width and spacing are recommended. figure 28. arrangement of signal tracks 5mil 5mil 5mil 5mil 5mil 5mil 5mil gnd d+ gnd d? ? try to minimize the number of copper/solder joints, because they can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and d ? paths and at the same temperature. thermocouple effects are not a major problem because 1 c corresponds to approximately 200 v, a n d thermocouple voltages are approximately 3 v/ c of temperature difference. unless there are two thermocouples with a big temperature differential between them, the voltages should be much less than 200 v. ? place a 0.1 f bypass capacitor close to the adm1033. ? if the distance to the remote sensor is more than 8 inches, twisted pair cable is recommended. this works up to about 6 feet to 12 feet. ? for very long distances (up to 100 feet), use shielded twisted pair such as belden #8451 microphone cable. connect the twisted pair to d+ and d ? and the shield to gnd, close to the adm1033. leave the remote end of the shield unconnected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor c1 may be reduced or removed. in any case, the total shunt capacitance should never exceed 1000 pf. noise filtering for temperature sensors operating in noisy environments, common practice is to place a capacitor across the d+ and d ? pins to help combat the effects of noise. however, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pf. while this capacitor reduces the noise, it does not eliminate it, making it difficult to use the sensor in a very noisy environment. the adm1033 has a major advantage over other devices when it comes to eliminating the effects of noise on the external sensor. the series resistance cancellation feature allows a filter to be constructed between the external temperature sensor and the part. the effect of any filter resistance seen in series with the remote sensor is automatically cancelled from the temperature.
adm1033 http://onsemi.com 16 the construction of a filter allows the adm1033 and the remote temperature sensor to operate in noisy environments. figure 29 shows a low ? pass r ? c ? r filter with the following values: r = 100 and c = 1 nf. this filtering reduces both common ? mode noise and differential noise. figure 29. filter between remote sensor and adm1033 d+ 1nf 100 ? remote temperature sensor d? 100 ? limits, status registers, and interrupts high and low limits are associated with each measurement channel on the adm1033. these can form the basis of system status monitoring. a status bit can be set for any out ? of ? limit condition and detected by polling the device. alternatively, smbusalert s can be generated to flag a processor or microcontroller of an out ? of ? limit condition. 8 ? bit limits the following is a list of all the 8 ? bit limits on the adm1033: table 11. temperature limit registers register description default 0x0b local high limit 0x8b (75 c) 0x0c local low limit 0x54 (20 c) 0x0d local therm limit 0x95 (85 c) 0x0e remote 1 high limit 0x8b (75 c) 0x0f remote 1 low limit 0x54 (20 c) 0x10 remote 1 therm limit 0x95 (85 c) table 12. therm limit registers register description default 0x19 therm % limit 0xff default out ? of ? limit comparisons the adm1033 measures all parameters in a round ? robin format and sets the appropriate status bit for out ? of limit conditions. comparisons are made differently, depending on whether the measured value is compared to a high or low limit. high limit: comparison performed low limit: < comparison performed analog monitoring cycle time the analog monitoring cycle time begins on powerup, or, if monitoring has been disabled, by writing a 1 to the monitor/ stby bit of configuration register 1, (address 0x01). the adc measures each one of the analog inputs in turn; as each measurement is completed, the result is automatically stored in the appropriate value register. the round ? robin monitoring cycle continues unless it is disabled by writing a 0 to the monitor/stby bit (bit 0) of configuration register 1 (address 0x01). the adc performs round ? robin conversions and takes 11 ms for the local temperature measurement and 32 ms for each remote temperature measurement with averaging enabled. the total monitoring cycle time for the average temperatures is therefore nominally. 32 11 43 ms (eq. 2) once the conversion time elapses, the round robin starts again. for more information, refer to the conversion rate register section. fan tach measurements take place in parallel and are not synchronized with the temperature measurements in any way. status registers the results of limit comparisons are stored in the status registers. a 1 represents an out ? of ? limit measurement; a 0 represents an in ? limit measurement. the status registers are located at addresses 0x4f to 0x51. if the measurement is outside its limits, the corresponding status register bit is set to 1. it remains set at 1 until the measurement falls back within its limits and it is read or until an ara is completed. poll the state of the various measurements by reading the status registers over the serial bus. if bit 0 (alert low) of status register 3 (address 0x51) is set, this means that the alert output has been pulled low by the adm1033. pin 14 can be configured as a smbusalert output. this automatically notifies the system supervisor of an out ? of ? limit condition. reading the status register clears the status bit as long as the error condition is gone. status register bits are sticky. whenever a status bit is set due to an out ? of ? limit condition, it remains set even after the triggering event has gone. the only way to clear the status bit is to read the status register (after the event has gone). interrupt mask registers (reg. 0x08, reg. 0x09, reg. 0x0a) allow individual interrupt sources to be masked from causing an alert . however, if one of these masked interrupt sources goes out of limit, its associated status bit is set in the status register. table 13. interrupt status register 1 (reg. 0x4f) bit # name description 7 lh 1 = local high temperature limit has been exceeded. 6 ll 1 = local low temperature limit has been exceeded. 5 r1h 1 = remote 1 high temperature limit has been exceeded. 4 r1l 1 = remote 1 low temperature limit has been exceeded. 3 r1d 1 = remote 1 diode error; indicates an open or short on the d1+/d1 ? pins. 2 unused reserved. 1 unused reserved. 0 unused reserved.
adm1033 http://onsemi.com 17 table 14. status register 2 (reg. 0x50) bit # name description 7 lt 1 = local therm temperature limit has been exceeded. 6 r1t 1 = remote 1 therm temperature limit has been exceeded. 5 unused reserved. 4 t% 1 = therm % on ? time limit has been exceeded. 3 ta 1 = one of the therm limits has been exceeded; and the therm output signal has been asserted. 2 ts 1 = therm state. indicates the therm pin is active; clears on a read if therm is not active. does not generate an alert in alert comp mode. 1 res reserved. 0 res reserved. table 15. status register 3 (reg. 0x51) bit # name description 7 f1s 1 = fan 1 has stalled. 6 fa 1 = fan alarm speed. fan1 and fan 2 are running at alarm speed. 5 res reserved. 4 res reserved. 3 res reserved. 2 res reserved. 1 res reserved. 0 alert 1 = alert low; indicates the alert line has been pulled low. alert interrupt behavior the adm1033 generates an alert whenever an out ? of ? limit measurement is made (if it is not masked out). the user can also detect out ? of ? limit conditions by polling the adm1033 status registers. it is important to note how the smbus alert output behaves when writing interrupt handler software. the alert output on the adm1033 can be programmed to operate in either smbusalert mode or in comp mode. in smbusalert mode, the alert output remains low until the measurement falls back within its programmed limits and either the status register is read or an ara is completed. in comp mode, the alert output automatically resets once the temperature measurement falls back within the programmed limits. configuring the alert output for smbusalert mode, set the alert configuration bit (bit 3) of the configuration register 1 (address 0x01) to 0. in smbusalert mode, a status bit is set when a measurement goes outside of its programmed limit. if the corresponding mask bit is not set, the alert output is pulled low. if the measured value falls back within the limits, the alert output remains low until the corresponding status register is read or until an ara is completed (as long as no other measurement is outside its limits). for comp mode, set the alert configuration bit (bit 3) of configuration register 1 (address 0x01) to1. in comp mode, the alert output is automatically pulled low when a measurement goes outside its programmed limits. once the measurement falls back within its limits (and assuming no other measurement channel is outside its limits), the alert output is automatically pulled high again. the main difference between the two modes is that the smbusalert does not reset without software intervention, whereas the comp mode alert output automatically resets. figure 30. alert comparator and smbusalert outputs alert, 70 c temperature limits time cleared on read alert comp smbusalert handling smbusalert interrupts to prevent tie ? ups due to service interrupts, follow these steps: 1. detect an smbus assertion. 2. enter the interrupt handler. 3. read the status register to identify the interrupt source. 4. mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (from reg. 0x08 to reg. 0x0a). 5. take the appropriate action for a given interrupt source. 6. exit the interrupt handler. 7. periodically poll the status register. if the interrupt status bit clears, reset the corresponding interrupt mask bit to 0. the smbusalert output and status bits then behave as shown in figure 31.
adm1033 http://onsemi.com 18 figure 31. handling smbusalert temperature interrupt mask bit cleared (smbusalert rearmed) cleared on read (temp below limit) interrupt mask bit set high limit smbusalert ?sticky? status bit temp back in limit (status bit stays set) interrupt masking register mask registers 1, 2, and 3 are located at addresses 0x08, 0x09, and 0x0a. these allow individual interrupt sources to be masked out to prevent the smbusalert interrupts. masking the interrupt source prevents only the smbusalert from being asserted; the appropriate status bit is still set as normal. table 16. mask register 1 (reg. 0x08) bit # name description 7 lh 1 masks the alert for the local high temperature. 6 ll 1 masks the alert for the local low temperature. 5 r1h 1 masks the alert for the remote 1 high temperature. 4 r1l 1 masks the alert for the remote 1 low temperature. 3 r1d 1 masks the alert for the remote 1 diode errors. 2 res reserved. 1 res reserved. 0 res reserved. table 17. mask register 2 (reg. 0x09) bit # name description 7 res reserved. 6 res reserved. 5 res reserved. 4 t% 1 masks the alert for the therm % on ? time limit. 3 ta 1 masks the alert for the therm limit being exceeded and the therm output signal being asserted. 2 ts 1 masks the alert for the therm state; has no effect on alert in alert comp mode. 1 res reserved. 0 res reserved. table 18. mask register 3 (reg. 0x0a) bit # name description 7 f1s 1 mask the alert for fan 1 stalling 6 fa 1 mask the alert for fans at alarm speed 5 res reserved. 4 res reserved. 3 res reserved. 2 res reserved. 1 res reserved. 0 res reserved. fan_fault output the fan_fault output signals when one or both of the fans stall. pin 8, the f an_fault output, is a dual ? function pin. it defaults to being a fan_fault output but can be reconfigured as an analog input reference for the therm input. to do this, set the fan_fault /ref (bit 7) in configuration register 4 (address 0x04) to 1. fault queue the adm1033 has a programmable fault queue option that lets the user program the number of out ? of ? limit measurements allowable before generating an alert . the fault queue affects only temperature measurement channels and is only operational in smbusalert mode. it performs some simple filtering, which is particularly useful at the higher conversion rates (16, 32, and 64 conversions per second), where averaging is not carried out. there is a queue for each of the temperature channels. if l (the number programmed to the fault queue) or more consecutive out ? of ? limit readings are made on the same temperature channel, the fault queue fills, and the smbusalert output triggers. to fill the fault queue, one needs l or more consecutive out of limits on the internal temperature channel; l or more consecutive out ? of ? limits on the external 1 temperature channel; or l or more consecutive out ? of ? limits on the external 2 temperature channel. the fault queue is independent of the state of the bits in the alert status registers. table 19. fault queue address 0x06 bits <3:0> fault queue 000x 1 001x 2 01xx 3 1xxx 4 to reset the fault queue, do one of the following: ? smbus ara command ? read status register 1 ? power ? on reset the smbusalert clears, even if the condition that caused the smbusalert remains. the smbusalert is reasserted if the fault queue fills up.
adm1033 http://onsemi.com 19 conversion rate register the adm1033 makes up to 64 measurements per second. however, for the sake of reduced power consumption and better noise immunity, users may run the adm1033 at a slower conversion rate. better noise immunity results from the averaging that occurs at the slower conversion rates. averaging does not occur at rates of 16, 32, or 64 conversions per second. table 20 lists the available conversion rates. note that the current round ? robin loop must be finished for conversion rates changes to take ef fect. table 20. conversion rates code conversion rate 0x00 0.0625 0x01 0.125 0x02 0.25 0x03 0.5 0x04 1 0x05 2 0x06 4 0x07 8 0x08 16 0x09 32 0x0a 64 0x0b to 0xff reserved therm i/o timer and limits pin 7 can be configured as either an input or output. as an output it is asserted low to signal that the measured temperature has exceeded preprogrammed temperature limits. the output is automatically pulled high again when the temperature falls below the therm ? hys limit. the value of hysteresis is programmable in register 0x1a. therm is enabled as an output by default on powerup. figure 32. therm behavior temperature limits time therm, 85 c therm therm ? hyst, 80 c once the therm limits are exceeded, the fans are boosted to full speed, that is, as long as the boost disable bit (bit 1) is not set in configuration register 2 (address 0x02). to configure therm as an input, the user must set the therm timer bit (bit 2) of configuration register 1 (address 0x01) to 1. (it no longer operates as an output.) the adm1033 can then detect when the therm input is asserted low. this may be connected to a trip point temperature sensor or to the fan_fault prochot output of a cpu. with processor core voltages reducing all the time, the threshold for the agtl + prochot output also reduces down as new processors become available. the default threshold on the input is the normal cmos threshold. however , pin 8 (fan_fault /ref) can also be reconfigured as a ref input. this is done by setting bit 7 (fan_fault /ref) in configuration register 4 (address 0x04). connect the processor v ccp to this input to provide a reference for the therm input. the resulting therm threshold is 0.75xv ccp , which is the correct threshold for an agtl+ signal. the adm1033 also measures assertion times on the therm input as a percentage of a time window. this time window is programmable in configuration register 4 (address 0x04) by using bits <6:4> (therm % time window). values between 0.25 seconds and 8 seconds are programmable. the assertion time as a percentage of the time w indow is stored in the therm % on ? time register (address 0x4e). a therm % limit is also associated with this register. once the measured percentage exceeds the percentage limit, the therm % exceeded bit (bit 4) in status register 2 (address 0x50) is asserted and an alert is generated, that is, if the mask bit is not set. if the limit is set to 0x00, an alert is generated on the first assertion. if the limit is set to 0xff, an alert is never generated. this is because 0xff corresponds to the therm input, which is asserted continuously. table 21. conversion rates code therm % on ? time window 000 0.25 s 001 0.5 s 010 1 s 011 2 s 100 4 s 101 8 s 110 8 s 111 8 s when therm is configured as an input only, setting the enable therm events bits in configuration register 4 allows pin 7 to operate as an i/o. the user can configure the therm pin to be pulled low as an output whenever the local temperature exceeds the local therm limit. to do this, set the enable local therm events bit (bit 0) of configuration register 4 (address 0x04). the user can also configure the therm pin to be pulled low as an output whenever the remote 1 temperature exceeds the remote 1 therm limit. set the enable remote 1 therm events bit (bit 1) of configuration register 4 (address 0x04).
adm1033 http://onsemi.com 20 therm % limit register the therm % limit is programmed to register 0x19. an alert is generated, if therm is asserted for longer than the programmed percentage limit. the limit is programmed as a percentage of the chosen time window. therm % limit register is an 8 ? bit register. 0x00 = 0% 0xff = 100% therefore, 1 lsb = 0.39%. example: if a time window of 8 seconds is chosen, and an alert is to be generated if therm is asserted for more than 1 second, program the following value to the limit register: % limit = 1/8 x 100 = 12.5% 12.5% / 0.39% = 32d = 0x20 = 0010 0000 an alert is generated if the therm limit is exceeded after the time window has elapsed, assuming it is not masked. fan drive signal the adm1033 contols the speed of up to one cooling fan. varying the duty cycle (on/off time) of a square wave applied to the fan varies the speed of the fan. the adm1033 uses a control method called synchronous speed control, in which the pwm drive signal applied to the fan is synchronized with the fan?s tach signal. see the synchronous speed control section for more information. the external circuitry required to drive the fan is very simple. a single n ? channel mosfet is the only drive device required. the specifications of the mosfet depend on the maximum current required by the fan and the gate voltage drive (v gs < 3.0 v for direct interfacing to the drive pin). v gs can be greater than 3.0 v, as long as the pullup on the gate is tied to 5.0 v. the mosfet should also have a low on ? resistance to ensure that there is no significant voltage drop across the fet. a high on ? resistance reduces the voltage applied across the fan and therefore the maximum operating speed of the fan. figure 33 shows a scheme for driving a 3 ? wire fan. figure 33. interfacing a 3 ? wire fan to the adm1033 by using an n ? channel mosfet 12v 12v fan 1n4148 q1 ndt3055l adm1033 drive tach tach 3.3v 100k 10k 10k 4.7k 12v figure 33 uses a 10 k pullup resistor for the tach signal. this assumes that the tach signal is an open collector from the fan. in all cases, the fan?s tach signal must be kept below 5.0 v maximum to prevent damaging the adm1033. if in doubt as to whether a fan has an open ? collector or totem pole tach output, use one of the input signal conditioning circuits shown in the fan inputs section. when designing drive circuits with transistors and fets, make sure that the drive pins are not required to source current and that they sink less than the maximum current specified here. synchronous speed control the adm1033 drives the fan by using a control scheme called synchronous speed control. in this scheme, the pwm drive signal applied to the fan is synchronized with the tach signal. accurate and repeatable fan speed measurements are the main benefits. the fan is allowed to run reliably at speeds as low as 30 percent of the full capability. the drive signal applied to the fan is synchronized with the tach signal. the adm1033 switches on the drive signal and waits for a transition on the tach signal. when a transition takes place on the tach signal, the pwm drive is switched off for a period of time called toff . the drive signal is then switched on again. the toff time is varied in order to vary the fan speed. if the fan is running too fast, the toff time is increased. if the fan is running too slow, the toff time is decreased. since the drive signal is synchronized with the tach signal, the frequency with which the fan is driven depends on the current speed of the fan and the number of poles in it. figure 34 shows how the synchronous speed drive signal works. the ideal tach signal is the tach signal that would be output from the fan if power were applied 100 percent of the time. it is representative of the actual speed of the fan. the actual tach signal is the signal the user would see on the tach output from the fan if the user were to put a scope on it. in effect, the actual tach signal is the ideal tach signal chopped with the drive signal.
adm1033 http://onsemi.com 21 figure 34. drive signal by using synchronous control ideal tach pole transition points dash = tach floats high by pull-up resistor solid = true tach when fan is powered drive actual tach t off t pole fan inputs pin 2 is a tach input intended for fan speed measurement. this input is open ? drain. signal conditioning on the adm1033 accommodates the slow rise and fall time of typical tachometer outputs. the maximum input signal range is from 0 v to 5.0 v, even when v cc is less than 5.0 v. in the event that these inputs are supplied from fan outputs exceeding 0 v to 5.0 v, either resistive attenuation of the fan signal or diode clamping must be used to keep the fan inputs within an acceptable range. figure 35 to figure 38 show examples of possible fan input circuits. if the fan tach has a resistive pullup to v cc , it can be connected directly to the fan output. figure 35. fan with tach pullup to +v cc 5.0 v or 12 v fan drive x fan speed counter adm1033 tach x pullup 4.7k typ tach output v cc v cc 100k typ if the fan output has a resistive pullup to 12 v (or another voltage greater than 5.0 v), the fan output can be clamped with a zener diode, as shown in figure 36. the zener voltage should be chosen so that it is greater than v ih but less than 5.0 v. allowing for the voltage tolerance of the zener, a value of between 3.0 v and 5.0 v is suitable. figure 36. fan with tach pullup to voltage > 5.0 v, clam p ed with zener diode 5.0 v or 12 v fan drive x fan speed counter adm1033 tach x pullup 4.7k typ tach output v cc v cc 100k typ zd1* *choose zd1 voltage approximately 0.8 v cc if the fan has a strong pullup (less than 1 k to +12 v) or a totem ? pole output, a series resistor can be added to limit the zener current, as shown in figure 37. alternatively, a resistive attenuator may be used, as shown in figure 38. r1 and r2 should be chosen such that (eq. 3) 2.0 v v pullup r2 (r pullup r1 r2) 5.0 v the fan inputs have an input resistance of nominally 160 k to ground. this should be taken into account when calculating resistor values. with a pullup voltage of 12 v and pullup resistor less than 1 k , suitable values for r1 and r2 would be 100 k and 47 k . this gives a high input voltage of 3.83 v. figure 37. fan with strong tach. pullup to >v cc or totem ? pole out p ut, clam p ed with zener and resistor 12 v adm1033 fan speed counter fan(0?7) pullup typ <1 k or totem pole v cc * choose zd1 voltage approximately 0.8 v cc
adm1033 http://onsemi.com 22 figure 38. fan with strong tach. pullup to >v cc or totem ? pole output, attenuated with r1/r2 12 v fan speed counter adm1033 fan(0?7) <1 k tach output v cc r1* r2 *see text fan speed measurement the fan counter does not count the fan tach output pulses directly. this is because the fan may be spinning at less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on ? chip 81.92 khz oscillator into the input of a 16 ? bit counter for one complete revolution of the fan. therefore, the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. the number of poles in the fan must be programmed in configuration register 3 (address 0x03). bits <3:0> set the number of poles for fan 1, and bits <7:4> set the number of poles for fan 2. this number must be an even number only, because there cannot be an uneven number of poles in a fan. a tach period is output for every two poles. therefore, the number of poles must be known so that the adm1033 can measure for a full revolution. figure 39 shows the fan speed measurement period, assuming that the fan outputs an ideal tach signal. in reality, the tach signal output by the fan is chopped by the drive signal. however, since the drive and the tach signal are synchronized, there is enough information available for the adm1033 to measure the fan speed accurately. figure 39. fan speed measurement for a 4 ? pole fan clock ideal tach fan measurement period fan speed measurement registers these 16 ? bit measurements are stored in the tach value registers. table 22. tach value registers register description default 0x4a tach1 period, lsb 0xff 0x4b tach1 period, msb 0xff 0x4c tach2 period, lsb 0xff 0x4d tach2 period, msb 0xff reading fan speed reading back fan speeds involves a 2 ? register read for each measurement. the low byte should be read first. this freezes the high byte until both high and low byte registers have been read, preventing erroneous fan speed measurement readings. the fan tachometer reading registers report back the number of 12.2 s period clocks (81.92 khz oscillator) gated to the fan speed counter, for one full rotation of the fan, assuming the correct number of poles is programmed. since the adm1033 essentially measures the fan tach period, the higher the count value, the slower the actual fan speed. a 16 ? bit fan tach reading of 0xffff indicates that the fan has stalled or is running very slowly (< 75 rpm). calculating fan speed fan speed in rpm is calculated as follows. this assumes that the number of poles programmed in the configuration register 3 (address 0x03) is correct for both fans. fan speed (rpm) = (81920 x 60)/fan tach reading where: fan tach reading = 16 ? bit fan tachometer reading example: tach1 high byte (reg. 0x4a) = 0x17 tach1 low byte (reg. 0x4b) = 0xff what is fan 1 speed in rpm? fan 1 tach reading = 0x17ff = 6143d rpm = (f x 60) / fan 1 tach reading rpm = (81920 x 60) / 6143 fan speed = 800 rpm alarm speed the fan alarm speed (bit 6) in status register 3 (address 0x51) is set whenever the fan runs at alarm speed. this occurs if the device is programmed to run the fan at full speed whenever the therm temperature limits are exceeded. the device runs at alarm speed, for example, if the boost disable bit (bit 1) of the configuration 2 register (address 0x02) is not set to 1.
adm1033 http://onsemi.com 23 fan response register the adm1033 fan speed controller operates by reading the current fan speed, comparing it with the programmed fan speed, and then updating the drive signal applied to the fan. the rate at which the adm1033 looks at and updates the drive signal is determined by the fan response register. different fans have different inertias and respond to a changing drive signal more or less quickly than others. the fan response register allows the user to tailor the adm1033 to a particular fan to prevent situations like overshoot. the user programs the number of updates the adm1033 can make to the drive signal per second. table 23 lists the available options. table 23. fan response codes code update rate 000 1.25 updates/second 001 2.5 updates/second = default 010 5 updates/second 011 10 updates/second 100 20 updates/second 101 40 updates/second 110 80 updates/second 111 160 updates/second table 24. conversion rates bit # function 7 reserved <6:4> reserved 3 reserved <2:0> fan 1 response look ? up table: modes of operation the adm1033 look ? up table has two different modes of operation used to determine the behavior of the system: ? manual mode ? look ? up table manual mode in manual mode, the adm1033 is under software control. the software can program the required fan speed value or the target fan speed to the adm1033, which then outputs that fan speed. programming target fan speed in this mode, the user programs the target fan speed as a tach count for n poles or a tach count for one full rotation of the fan, assuming the number of poles is programmed correctly in the configuration 3 register (address 0x03). use the following steps to program the target fan speed: 1. place the adm1033 into manual mode. set bit 7 (table/sw) of configuration register 1 (address 0x01) = 0. 2. program the target tach count (fan speed) using the following equation: tach count = (f x 60)/r where: f = clock frequency = 81.92 khz r = required rpm value example 1 : if the desired speed for fan 1 is 5000 rpm, program the following value to the tach count registers: tach count = (f x 60)/5000 tach count = 983d = 0x03d7 example 2: if the desired speed for fan 2 is 3500 rpm, program the following value to the tach pulse period registers: tach count = (f x 60)/3500 tach count = 1404d = 0x057c table 25. registers to be programmed fan description address value fan 1 look ? u p table fs1, lsb 0x2a 0xd7 fan 1 look ? u p table fs1, msb 0x2b 0x03 look ? up table the adm1033 allows the user to program a temperature ? to ? fan speed profile. there are 24 registers in the look ? up table; 8 for temperature and 16 for target fan speed (each target fan speed is two registers). in total, there are eight available points. there are two options when programming the look ? up table. the adm1033 can be programmed to make the fan speed run at discrete speeds and jump to the new fan speed once the temperature threshold is crossed. or, it can linearly ramp the tach count between the two temperature thresholds. figure 40 and figure 41 show what the look ? up table looks like if all eight points are used on the one curve. figure 40 shows the transfer curve when the fan is programmed to run at discrete speeds. the adm1033 spins the fan at its new speed once a threshold is crossed. figure 40. programming the look ? u p table in discreet fan speeds mode tach count 8 fan speed t1 t2 t3 t4 t5 t6 t7 t8 temperature tach count 7 tach count 6 tach count 5 tach count 4 tach count 3 tach count 2 tach count 1
adm1033 http://onsemi.com 24 figure 41 shows the transfer curve if the linear fan speeds option is chosen. at temperature t1, the fan runs at fan speed 1. as the temperature increases, the fan speed increases until it reaches fan speed 2 at t2. figure 41. programming the look ? up table in linear fan speeds mode tach count 8 fan speed t1 t2 t3 t4 t5 t6 t7 t8 temperature tach count 7 tach count 6 tach count 5 tach count 4 tach count 3 tach count 2 tach count 1 figure 42. programming two points on the look ? up table fan speed t1 t2 t (3 to 8) = c temperature tach count 2 to 8 tach count 1 once the temperature exceeds the highest temperature point in the look ? up table, the fan speed remains at the highest speed until the temperature drops below the t7 temperature value. when the look ? up table is split in two, the same applies. if the temperatures in t1 to t8 are not programmed in succession, the fan speed moves to the next highest programmed temperature as the temperature increases. similarly, when the temperature decreases, it ignores programmed higher temperatures and jumps to the next lower temperature. therefore, the temperature ? to ? fan speed profile for increasing and decreasing temperature can be different. when programming the look ? up table, the user has the option to use between two and eight points for the fan. if the user just wants to program a transfer curve (and knows the starting temperature, minimum speed, maximum temperature, and maximum speed), then all the user needs to program are four parameters: t1, t2, fs1, and fs2. the remainder of the look ? up temperature thresholds should remain at their default values of +191 c. if required, the fs3 should be programmed with the same value as fs2 to give the flat curve, if required. or, the fan speeds can be left at the default value of 0. however, it is normal to program a therm limit as well. once this temperature is exceeded and the boost bit is set, the fan run to full speed. this overrides the look ? up table. table 26. look ? up table register address x temperature, x fsx, lsb fsx, msb 1 0x22 0x2a 0x2b 2 0x23 0x2c 0x2d 3 0x24 0x2e 0x2f 4 0x25 0x30 0x31 5 0x26 0x32 0x33 6 0x27 0x34 0x35 7 0x28 0x36 0x37 8 0x29 0x38 0x39 setting up the look ? up table in linear mode when discrete/linear speed (bit 2) is set to 1 (default), the tach count decreases linearly (and therefore the fan speed increases) with temperature. example: at temperature t x , the fans run at fs x and fan speed increases with temperature to fs x+1 at temperature t x+1 . alternatively, the fan can be run at discrete fan speeds. when discrete/linear speed (bit 2) is set to 0, the fan runs at a new speed once the temperature threshold is exceeded. setting which temperature channel controls a fan fan behavior register (address 0x07) bits <1:0> = drive1 behavior (d1b) the adm1033 can be configured so that fan 1 can be controlled by either the local temperature, or by the remote 1 temperatures. table 27. drive bhvr bits bits drive x bhvr 00 local temperature controls fan 01 remote 1 temperature controls fan 10 reserved 11 fan runs at full speed look ? up table hysteresis the user can program a hysteresis to be applied to the look ? up table. the advantage of this is apparent if the temperature is cycling around one of the threshold temperatures and causing the fan speed to switch between the two speeds, particularly when the look ? up table is configured in discrete mode. it would not be as important in the linear mode.
adm1033 http://onsemi.com 25 table 28. programming the hysteresis code hysteresis value 0000 0000 0 c 0000 0001 1 c 0000 0010 2 c 0000 0101 5 c 0000 1000 8 c 0000 1111 15 c the look ? up table?s hysteresis register is at address 0x3a. a hysteresis value of between 0 c and 15 c can be programmed with a resolution of 1 c and applied to all the temperature thresholds. table 28 gives examples of values for programming. programming the therm limit for temperature channels therm is the absolute maximum temperature allowed on a temperature channel. above this temperature, a component such as the cpu or vrm may be operating beyond its safe operating limit. when the temperature measured exceeds therm , all fans are driven at full speed to provide critical system cooling. the fans remain running at full speed until the temperature drops below therm ? hysteresis. the hysteresis value is programmable; its default is 5 c. if the boost disable bit (bit 1) is set in configuration register 2, the fan do not run to full speed. the therm limit is considered the maximum worst ? case operating temperature of the system. exceeding any therm limit runs the fan at full speed, a condition with very negative acoustic effects. this limit should be set up as a fail ? safe and not exceeded under normal system operating conditions. the therm temperature limit registers are listed in table 29. table 29. therm hysteresis registers address description default 0x0d local therm limit 0x95 (85 c) 0x10 remote 1 therm limit 0x95 (85 c) the therm hysteresis register is at address 0x1a. a hysteresis value is programmed and applied to all two temperature channels; local and remote 1. a therm hysteresis value of between 0 c and 15 c can be programmed with a resolution of 1 c. table 33 gives some examples. table 30. programming therm hysteresis code hysteresis value 0000 0000 0 c 0000 0001 1 c 0000 0010 2 c 0000 0101 5 c = default 0000 1000 8 c 0000 1111 15 c xor tree test mode the adm1033 includes an xor tree test mode. this is useful for in circuit test equipment at board level testing. by applying stimulus to the pins included in the xor test, it is possible to detect opens or shorts on the system board. figure 43 shows the signals that are exercised in the xor tree test mode. the xor tree test is enabled by setting the xor bit (bit 3) in configuration 4 register (0x04). figure 43. xor tree test fan_fault/ref tach1 drive2 therm location alert drive1 lock bit setting the lock bit (bit 6) of configuration register 1 (address 0x01) makes all the lockable registers read ? only. these registers remain read ? only until the adm1033 is powered down and back up again. for more information on which registers are lockable, see table 31. sw reset setting the software reset bit (bit 0) of configuration register 2 (address 0x02) resets all software resettable bits to their default value. for more information on resetting registers and their default values, see table 31 to table 65.
adm1033 http://onsemi.com 26 table 31. adm1033 registers address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lock ? able? 0x00/80 r/w #bytes/block read 7 6 5 4 3 2 1 0 0x20 y 0x01/81 r/w configuration 1 table/sw lock sda scl alert timer avg mon 0x01 y 0x02/82 r/w configuration 2 rr res cs cs res d/l bd reset 0x84 y 0x03/83 r/w configuration 3 #fp2 #fp2 #fp2 #fp2 #fp1 #fp1 #fp1 #fp1 0x04 y 0x04/84 r/w configuration 4 ff/ref % t % t % t xor res r1tm ltm 0x00 y 0x05/85 r/w conversion rate res res res res conv conv conv conv 0x07 y 0x06/86 r/w fault queue res res res res fq fq fq fq 0x01 y 0x07/87 r/w fan behavior res f1 off res res res res d1b d1b 0x01 y 0x08/88 r/w mask 1 lh ll r1h r1l r1d r2h r2l r2d 0x50 n 0x09/89 r/w mask 2 res res res % t ta ts res res 0x18 n 0x0a/8a r/w mask 3 f1s fa f2s res res res res res 0x00 n 0x0b/8b r/w local high limit 7 6 5 4 3 2 1 0 0x8b n 0x0c/8c r/w local low limit 7 6 5 4 3 2 1 0 0x54 n 0x0d/8d r/w local therm limit 7 6 5 4 3 2 1 0 0x95 y 0x0e/8e r/w remote 1 high limit 7 6 5 4 3 2 1 0 0x8b n 0x0f/8f r/w remote 1 low limit 7 6 5 4 3 2 1 0 0x54 n 0x10/90 r/w remote 1 therm limit 7 6 5 4 3 2 1 0 0x95 y 0x16/96 r/w local offset 7 6 5 4 3 2 1 0 0x00 y 0x17/97 r/w remote 1 offset 7 6 5 4 3 2 1 0 0x00 y 0x19/99 r/w therm % limit 7 6 5 4 3 2 1 0 0xff y 0x1a/9a r/w therm hysteresis res res res res hys hys hys hys 0x05 y 0x22/a2 r/w look ? up table t1 7 6 5 4 3 2 1 0 0xff y 0x23/a3 r/w look ? up table t2 7 6 5 4 3 2 1 0 0xff y 0x24/a4 r/w look ? up table t3 7 6 5 4 3 2 1 0 0xff y 0x25/a5 r/w look ? up table t4 7 6 5 4 3 2 1 0 0xff y 0x26/a6 r/w look ? up table t5 7 6 5 4 3 2 1 0 0xff y 0x27/a7 r/w look ? up table t6 7 6 5 4 3 2 1 0 0xff y 0x28/a8 r/w look ? up table t7 7 6 5 4 3 2 1 0 0xff y 0x29/a9 r/w look ? up table t8 7 6 5 4 3 2 1 0 0xff y 0x2a/aa r/w look ? up table, fs1 7 6 5 4 3 2 1 0 0xff y 0x2b/ab r/w look ? up table, fs1 15 14 13 12 11 10 9 8 0xff y 0x2c/ac r/w look ? up table, fs2 7 6 5 4 3 2 1 0 0xff y 0x2d/ad r/w look ? up table, fs2 15 14 13 12 11 10 9 8 0xff y 0x2e/ae r/w look ? up table, fs3 7 6 5 4 3 2 1 0 0xff y 0x2f/af r/w look ? up table, fs3 15 14 13 12 11 10 9 8 0xff y 0x30/b0 r/w look ? up table, fs4 7 6 5 4 3 2 1 0 0xff y 0x31/b1 r/w look ? up table, fs4 15 14 13 12 11 10 9 8 0xff y 0x32/b2 r/w look ? up table, fs5 7 6 5 4 3 2 1 0 0xff y 0x33/b3 r/w look ? up table, fs5 15 14 13 12 11 10 9 8 0xff y 0x34/b4 r/w look ? up table, fs6 7 6 5 4 3 2 1 0 0xff y 0x35/b5 r/w look ? up table, fs6 15 14 13 12 11 10 9 8 0xff y 0x36/b6 r/w look ? up table, fs7 7 6 5 4 3 2 1 0 0xff y 0x37/b7 r/w look ? up table, fs7 15 14 13 12 11 10 9 8 0xff y 0x38/b8 r/w look ? up table, fs8 7 6 5 4 3 2 1 0 0xff y 0x39/b9 r/w look ? up table, fs8 15 14 13 12 11 10 9 8 0xff y 0x3a/ba r/w look ? up table hys- teresis res res res res hys hys hys hys 0x05 y
adm1033 http://onsemi.com 27 table 31. adm1033 registers address lock ? able? default bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 description r/w 0x3c/bc r/w fan response res res res res res f1 f1 f1 0x01 y 0x3d/bd r device id 7 6 5 4 3 2 1 0 0x34 n 0x3e/be r company id 7 6 5 4 3 2 1 0 0x41 n 0x3f/bf r revision register 7 6 5 4 3 2 1 0 0x02 n 0x40/c0 r local temperature 4 3 2 1 0 res res res 0x00 n 0x41/c1 r local temperature 12 11 10 9 8 7 6 5 0x00 n 0x42/c2 r remote 1 temp 4 3 2 1 0 res res res 0x00 n 0x43/c3 r remote 1 temp 12 11 10 9 8 7 6 5 0x00 n 0x4a/ca r tach1 period 7 6 5 4 3 2 1 0 0xff n 0x4b/cb r tach1 period 15 14 13 12 11 10 9 8 0xff n 0x4e/ce r therm % ontime 7 6 5 4 3 2 1 0 0x00 n 0x4f/cf r status 1 lh ll r1h r1l r1d res res res 0x00 n 0x50/d0 r status 2 lt r1t res % t ta ts res res 0x00 n 0x51/d1 r status 3 f1s fa res res res res res alert 0x00 n table 32. register 0x00, # bytes/block read, por = 0x20, lock = y, s/w reset = y bit name r/w description <7:0> # bytes block read r/w block reads are # bytes/block read long. the maximum is 32 bytes, the smbus transaction limit. table 33. register 0x01, configuration register 1, power ? on default 0x01, lock = y, s/w reset = y bit name r/w description 7 table/sw con r/w set this bit to 1 to place the fan speed under the control of the look ? up table. when this bit is 0, the adm1033 is in software/manual control mode. default = 0. 6 lock bit r/w set this bit to 1 to prevent the user from writing to the adm1033 registers. 1 = adm1033 registers locked. 0 = adm1033 registers unlocked. default = 0. 5 sda timeout r/w 1 = sda timeout enabled. 0 = sda timeout disabled. default = 0. 4 scl timeout r/w 1 = scl timeout enabled. 0 = sdl timeout disabled. default = 0. 3 alert configuration r/w 0 = smbusalert . default = 0. 1 = alert _comp mode. 2 enable therm timer r/w 1 = timer enabled, 0 = timer disabled. this bit enables therm as an input. default = 0. 1 averaging off r/w this bit is used to disable averaging at the slower conversion rates (8 hz and slower). averaging is automatically disabled at the higher (16, 32, and 64 hz ) conversion rates. default = averaging on = 0. 0 monitor/stby r/w set bit to 1 to enable temperature monitoring. set bit to 0 to disable it. power ? on default = 1
adm1033 http://onsemi.com 28 table 34. register 0x02, configuration register 2, power ? on default 0x84, lock = y, s/w reset = y bit name r/w description 7 round robin r/w this bit enables the round ? robin mode. set this bit to 0 to put the adm1033 in single ? channel mode. the adc converts on one channel only, which is determined by the channel selector bits. default = round robin = 1. 6 reserved r/w reserved. <5:4> channel selector r/w this bit determines the channel on which the adc converts. 00 = local channel only 01 = remote 1 channel only 10 = reserved 11 = reserved 3 reserved r/w reserved. 2 discrete/linear speed r/w this bit determines whether the fans run at discrete speeds or at speeds that increase with temperature between the two thresholds. default = 1 = linear. 1 boost disable r/w set bit to 1 to prevent the fans from being boosted if either therm temperature or therm timer limits are exceeded. under these conditions, the fan runs at the previously calculated speed. default = 0. 0 sw reset r/w set this bit to 1 to reset the adm1033 registers to their default values, excluding the limit registers, offset registers, and look ? up table registers. this bit self ? clears. default = 0. table 35. register 0x03, configuration register 3, power ? on default 0x04, lock = y, s/w reset = y bit name r/w description <7:4> reserved r/w reserved. <3:0> #poles fan r/w write the number of poles in fan to this register. power ? on default = 4 poles = 100. this should always be an even number, because there cannot be an odd number of poles in a fan. table 36. register 0x04, configuration register 4, power ? on default 0x00, lock = y, s/w reset = y bit name r/w description 7 fan_fault /ref r/w this bit sets the function for pin 8. 0 = default = fan_fault output (therm input is cmos). 1 = reference input for therm . <6:4> therm % time window r/w these bits set the time window over which therm % is calculated. 000 = 0.25 second 001 = 0.5 second 010 = 1 second 011 = 2 seconds 100 = 4 seconds 101 = 8 seconds 110 = 8 seconds 111 = 8 seconds 3 xor test r/w set this bit to 1 to enable the xor connectivity test. 2 reserved r/w reserved. 1 enable remote 1 therm events r/w this bit enables therm assertions as an output. functions when the therm timer is enabled and the remote 1 temperature exceeeds its therm limit. 0 enable local therm events r/w this bit enables therm assertions as an output. functions when the therm timer is enabled and the local temperature exceeeds its therm limit.
adm1033 http://onsemi.com 29 table 37. register 0x05, configuration rate register, power ? on default 0x07, lock = y, s/w reset = y bit name r/w description 7 reserved r this bit is reserved for future use. do not write to this bit. <6:4> reserved r reserved. <3:0> conversion rate r/w these four bits set the conversion rate of the adm1033. changing these bits does not update the conversion rate until the start of the next round robin. 0000 = 0.0625 conversions/second 0001 = 0.125 conversions/second 0010 = 0.25 conversions/second 0011 = 0.5 conversions/second 0100 = 1 conversion/second 0110 = 4 conversions/second 0111 = 8 conversions/second = default 1000 = 16 conversions/second 1001 = 32 conversions/second 1010 = 64 conversions/second table 38. register 0x06, fault queue, power ? on default 0x01, lock = y, s/w reset = y bit name r/w description <7:4> unused r reserved. <3:0> fault queue length r/w these four bits set the fault queue (the number of out ? of ? limit measurements made before an alert is generated). 000x = 1 001x = 2 01xx = 3 1xxx = 4 table 39. register 0x07, fan behavior register, power ? on default 0x01, lock = y, s/w reset = y bit name r/w description 6 fan 1 off r/w set this bit to 1 to switch off fan 1. 5 res r reserved. 4 res r reserved. <1:0> drive1 bhvr r/w these bits determine which temperature source controls the drive1 output. 00 = local temperature controls drive1. 01 = remote 1 temperature controls drive1. 10 = remote 2 temperature controls drive1. 11 = drive1 full speed. table 40. register 0x08, mask register 1, power ? on default 0x50, lock = n, s/w reset = y bit name r/w description 7 local high r/w a 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. the status bit is not affected. default = 0. 6 local low r/w a 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. the status bit is not affected. default = 1. 5 remote 1 high r/w a 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. the status bit is not affected. default = 0. 4 remote 1 low r/w a 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. the status bit is not affected. default = 1. 3 remote 1 diode error r/w a 1 disables the corresponding interrupt status bit from causing the interrupt output to be set. the status bit is not affected. default = 0.
adm1033 http://onsemi.com 30 table 41. register 0x09, mask register 2, power ? on default 0x18, lock = n, s/w reset = y bit name r/w description <7:5> unused r unused. 4 therm % r/w a 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. the status bit is not affected. default = 1. 3 therm assert r/w a 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. the status bit is not affected. default = 0. 2 therm _state r/w a 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. the status bit is not affected. default = 0. this bit has no effect in alert comparator mode, because the corresponding status bit does not generate an alert in that mode. <1:0> unused r unused. table 42. register 0x0a, mask register 3, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description 7 fan 1 stalled r/w a 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. the status bit is not affected. default = 0. 6 fan alarm speed r/w a 1 disables the corresponding interrupt status bit, preventing it from causing the interrupt output. the status bit is not affected. default = 0. 4 reserved r reserved. default = 0. 3 reserved r reserved. default = 0. 2 reserved r reserved. default = 0. 1 reserved r reserved. default = 0. 0 reserved r reserved. default = 0. table 43. register 0x0b, local high limit, power ? on default 0x8b, lock = n, s/w reset = n bit name r/w description <7:0> local high limit r/w when the local temperature exceeds this temperature, the corresponding interrupt status bit is set. table 44. register 0x0c, local low limit, power ? on default 0x54, lock = n, s/w reset = n bit name r/w description <7:0> local low limit r/w when the local temperature falls below this temperature, the corresponding interrupt status bit is set. table 45. register 0x0d, local therm limit, power ? on default 0x95, lock = y, s/w reset = y bit name r/w description <7:0> local therm limit r/w when the local temperature exceeds this temperature, the corresponding status bit is set and the therm output is activated. table 46. register 0x0e, remote 1 high limit, power ? on default 0x8b, lock = n, s/w reset = n bit name r/w description <7:0> remote 1 high limit r/w when the remote 1 temperature exceeds this temperature, the corresponding interrupt status bit is set. table 47. register 0x0f, remote 1 low limit, power ? on default 0x54, lock = n, s/w reset = n bit name r/w description <7:0> remote 1 low limit r/w when the remote 1 temperature falls below this temperature, the corresponding interrupt status bit is set.
adm1033 http://onsemi.com 31 table 48. register 0x10, remote 1 therm limit, power ? on default 0x95, lock = y, s/w reset = n bit name r/w description <7:0> remote 1 therm limit r/w when the remote 1 temperature exceeds this temperature, the corresponding status bit is set and the therm output is activated. table 49. register 0x16, local offset register, power ? on default 0x00, lock = y, s/w reset = n bit name r/w description <7:0> local offset r/w allows a twos compliment offset to be automatically added to or subtracted from the local temperature measurement. resolution = 0.125 c. maximum offset from - 16 c to +15.875 c. default = 0. table 50. register 0x17, remote 1 offset register, power ? on default 0x00, lock = y, s/w reset = n bit name r/w description <7:0> remote 1 offset r/w allows a twos compliment offset to be automatically added to or subtracted from the remote 1 temperature measurement. resolution = 0.125 c. maximum offset from - 16 c to +15.875 c. default = 0. table 51. register 0x19, therm timer % limit, power ? on default 0xff, lock = y, s/w reset = n bit name r/w description <7:0> therm timer on % limit r/w if the therm is asserted for greater than this limit on the time window, the corresponding status bit is set. table 52. register 0x1a, therm hysteresis, power ? on default 0x05, lock = y, s/w reset = n bit name r/w description <7:4> reserved r reserved. <3:0> therm hysteresis r/w an unsigned therm hysteresis value, lsb = 1 c. once therm has been activated on a temperature channel, the therm limit ? hysteresis is deactivated if the temperature drops below therm .
adm1033 http://onsemi.com 32 table 53. look ? up table registers, lock = y, s/w reset = y register address r/w description power ? on default 0x22 r/w look ? up table, t1 0xff 0x23 r/w look ? up table, t2 0xff 0x24 r/w look ? up table, t3 0xff 0x25 r/w look ? up table, t4 0xff 0x26 r/w look ? up table, t5 0xff 0x27 r/w look ? up table, t6 0xff 0x28 r/w look ? up table, t7 0xff 0x29 r/w look ? up table, t8 0xff 0x2a r/w look ? up table, fs1, lsb 0xff 0x2b r/w look ? up table, fs1, msb 0xff 0x2c r/w look ? up table, fs2, lsb 0xff 0x2d r/w look ? up table, fs2, msb 0xff 0x2e r/w look ? up table, fs3, lsb 0xff 0x2f r/w look ? up table, fs3, msb 0xff 0x30 r/w look ? up table, fs4, lsb 0xff 0x31 r/w look ? up table, fs4, msb 0xff 0x32 r/w look ? up table, fs5, lsb 0xff 0x33 r/w look ? up table, fs5, msb 0xff 0x34 r/w look ? up table, fs6, lsb 0xff 0x35 r/w look ? up table, fs6, msb 0xff 0x36 r/w look ? up table, fs7, lsb 0xff 0x37 r/w look ? up table, fs7, msb 0xff 0x38 r/w look ? up table, fs8, lsb 0xff 0x39 r/w look ? up table, fs8, msb 0xff table 54. register 0x3a, look ? up table hysteresis, power ? on default 0x05, lock = y, s/w reset = y bit name r/w description <7:4> reserved r reserved. <3:0> look ? up table hysteresis r/w these bits determine the hysteresis applied to the temperature thresholds in the look ? up table. lsb size = 1 c. table 55. register 0x3c, fan response register, power ? on default 0x01, lock = y, s/w reset = y bit name r/w description 7 res r reserved. 3 res r reserved. <2:0> fan 1 response r/w these bits set the fan?s response in the fan speed control mode. 000 = 1.25 updates/second 001 = 2.5 updates/second = default 010 = 5 updates/second 011 = 10 updates/second 100 = 20 updates/second 101 = 40 updates/second 110 = 80 updates/second 111 = 160 updates/second table 56. register 0x3d, device id, power ? on default 0x34, lock = n, s/w reset = n bit name r/w description <7:0> device id r this read ? only value contains the device id, which is 0x34.
adm1033 http://onsemi.com 33 table 57. register 0x3e, company id, power ? on default 0x41, lock = n, s/w reset = n bit name r/w description <7:0> company id r this read ? only value contains the company id, which is 0x41. table 58. register 0x3f, revision register, power ? on default 0x02, lock = n, s/w reset = n bit name r/w description <7:0> revision id r this read ? only value contains the revision id. table 59. register 0x40/41, local temp registers, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description <4:0> local temperature lsb r this register contains the lsbs of the last measured local temperature value. resolution = 0.03125 c. <12:5> local temperature msb r this register contains the msbs of the last measured local temperature value. resolution = 1 c. table 60. register 0x42/43, remote 1 temp registers, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description <4:0> remote 1 temperature lsb r this register contains the lsbs of the last measured remote 1 temperature value. resolution = 0.03125 c. <12:5> remote 1 temperature msb r this register contains the lsbs of the last measured remote 1 temperature value. resolution = 1 c. table 61. register 0x4a/4b, tach1 period, power ? on default 0xff, lock = n, s/w reset = y bit name r/w description <7:0> fan 1 period count, lsb r this register contains the lsbs of the last measured fan 1 revolution count. <15:8> fan 1 period count, msb r this register contains the msbs of the last measured fan 1 revolution count. table 62. register 0x4e, therm % on ? time, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description <7:0> therm % on ? time r represents the % time of therm activity within the time window set by the configuration bits. table 63. register 0x4f, status 1, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description 7 local temp high r a 1 indicates that the local high limit has been tripped. 6 local temp low r a 1 indicates that the local low limit has been tripped. 5 remote 1 temp high r a 1 indicates that the remote 1 high limit has been tripped. 4 remote 1 temp low r a 1 indicates that the remote 1 low limit has been tripped. 3 remote 1 diode error r a 1 indicates that a short or an open has been detected on the remote 1 temperature channel. this test is completed once on each conversion.
adm1033 http://onsemi.com 34 table 64. register 0x50, status 2, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description 7 local therm r a 1 indicates that the local therm limit has been tripped. 6 remote 1 therm r a 1 indicates that the remote 1 therm limit has been tripped. 4 therm % exceeded r a 1 indicates that the therm signal has been asserted for longer than the programmed limit. clear on read. if therm % limit = 0x00 and therm is asserted, it is reasserted immediately. 3 therm asserted r a 1 indicates that the therm signal has been asserted low as an input only. 2 therm _state r a 1 indicates that the therm pin has been asserted low as an output. 1 reserved r reserved. 0 reserved r reserved. table 65. register 0x51, status register 3, power ? on default 0x00, lock = n, s/w reset = y bit name r/w description 7 fan 1 stalled r a 1 indicates that fan 1 has stalled. 6 fan alarm speed r a 1 indicates that the fans are running at full speed due to an alarm condition, for instance, when a therm temperature limit is exceeded. 4 reserved r reserved. 3 reserved r reserved. 2 reserved r reserved. 1 reserved r reserved. 0 alert low r a 1 indicates that the adm1033 has pulled the alert output pin low. this allows polling of a single status register to determine if an alert condition in any of the status registers has occurred. ordering information device number temperature range package type package option shipping ? adm1033arqz ? 40 c to +125 c 16 ? lead qsop rq ? 16 98 tube adm1033arqz ? reel ? 40 c to +125 c 16 ? lead qsop rq ? 16 2500 tape & reel adm1033arqz ? rl7 ? 40 c to +125 c 16 ? lead qsop rq ? 16 1000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *the ?z?? suffix indicates pb ? free part.
adm1033 http://onsemi.com 35 package dimensions qsop16 case 492 ? 01 issue o max millimeters g r ? b ? ? a ? l m 0.25 (0.010) t u ? t ? seating plane k d 16 pl c m 0.25 (0.010) t ba s s v n j m f 8 pl detail e detail e h x 45 rad. mold pin dim min max min inches a 4.80 4.98 0.189 0.196 b 3.81 3.99 0.150 0.157 c 1.55 1.73 0.061 0.068 d 0.20 0.31 0.008 0.012 f 0.41 0.89 0.016 0.035 g 0.64 bsc 0.025 bsc h 0.20 0.46 0.008 0.018 j 0.249 0.191 0.0098 0.0075 k 0.10 0.25 0.004 0.010 l 5.84 6.20 0.230 0.244 m 0 8 0 8 n 0 7 0 7 p 0.18 0.28 0.007 0.011 q 0.51 dia 0.020 dia r 0.64 0.89 0.025 0.035 u 0.64 0.89 0.025 0.035 v notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. the bottom package shall be bigger than the top package by 4 mils (note: lead side only). bottom package dimension shall follow the dimension stated in this drawing. 4. plastic dimensions does not include mold flash or protrusions. mold flash or protrusions shall not exceed 6 mils per side. 5. bottom ejector pin will include the country of origin (coo) and mold cavity i.d. 0 8 0 8 mark q p 0.013 x 0.005 dp. max rad. 0.005 ? 0.010 typ on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 adm1033/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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